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PRELIMINARY TECHNICAL DATA
a
Charge Pump Regulator & COM Driver for Color TFT Panel ADM8840 Preliminary Technical Data
FUNCTIONAL BLOCK DIAGRAM
-15V
FEATURES Programmable COM Driver to prevent Screen-Burn 3 Voltages (5.0V,15.0V,-15.0V) from one 3V Supply Power Efficiency optimised for use with TFT in mobile phones Low Quiescent Current Low Shutdown Current (<5uA) Shutdown Function APPLICATIONS Handheld Instruments TFT LCD Panels Cellular Phones
VOLTAGE INVERTER
C4+
C4 0.22 F
C9
0.22 F
C4-
ADM8840
TRIPLE VOLTAGE TRIPLER DOUBLE
+15V
C2+
C2 0.22 F
C8
0.22 F
C2C3+
C3
0.22 F
C3-
OSCILLATOR
TIMING GENERATOR
5VIN +5V
5VOUT
SHDN
C7
2.2 F
SHUTDOWN CONTROL
DISCHARGE
LDO VOLTAGE REGULATOR
VOUT
C1+
C6
4.7 F
CONTROL LOGIC
VOLTAGE DOUBLER
C1-
C1 3.3 F
C10 3.3 F
V CC
VOLTAGE ADDER
C5+
C5
3.3 F
C5DAC1_IN
DAC1_SD
VREF
GENERAL DESCRIPTION
ADD_OUT
The ADM8840 combines a charge pump regulator and a Common Line (COM) driver in a single chip solution for use in TFT LCD's. The device provides an LCD controller and grayscale DAC supply voltage of 5.0V (2%), 2 gate drive voltages of +15V and -15V and a COM driver voltage. This COM Driver voltage alternates the polarity of the Common line voltage every line (or every frame) on the display in order to prevent screen-burn occuring over time. The ADM8840 is powered by a single 3.0V supply. The ADM8840 has an internal 100KHz oscillator for driving the charge pumps. The COM Driver section of the ADM8840 can be used to generate the alternate frame or line inversion of the COM line of the LCD panel. The ADM8840 receives the COM clock from the controller with a frequency up to 10kHz and allows programmable conditioning of its amplitude and centre voltage through the use of on-board DAC's. This allows programmable elimination of display flicker caused by the COM inversion. The COM_OUT amplitude can be programmed from 4.0V to 7.0V in steps of 28mV. The COM_OUT centre voltage can be programmed to 0.9V to 2.8V in steps of 14mV.
8
CLK DATA
CS / LDAC
DAC 1
INT/EXT DAC 1
+ -
C11 4.7 F
SERIAL INTERFACE
8 DAC 2
INT/EXT DAC 2
TRANS_OUT
C12 4.7 F
COM_IN
LEVEL TRANSLATOR
POWER BUFFER
COM_OUT_AC
C13 4.7 F
+
DAC2_SD
COM_OUT
DAC2_IN
5.5k
C PANE L
22nF
GND
The ADM8840 provides power up sequencing of the -15V and +15V gate drive outputs, ensuring the -15V starts to power up before the +15V. The ADM8840 has a number of power save features, including low power Shutdown. The 5.0V output consumes the most power, so Power Efficiency is also maximised on this output with an oscillator enabling scheme (Green IdleTM). The ADM8840 is fabricated using CMOS technology for minimal power consumption. The part is packaged in a 32pin LFCSP package.
TM
Green Idle is a registered trademark of Analog Devices Inc.
REV. PrG 2/03
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P Box 9106, Norwood, MA 02062-9106, U.S.A. .O. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 Analog Devices, Inc., 2003
PRELIMINARY TECHNICAL DATA ADM8840
-15V
VOLTAGE INVERTER
C4+
C4 0.22 F
C9
0.22 F
C4-
ADM8840
C2+
+15V
C8 C2 0.22 F
0.22 F
TRIPLE VOLTAGE TRIPLER DOUBLE
C3-
C2C3+
C3
0.22 F
OSCILLATOR
TIMING GENERATOR
5VIN +5V
5VOUT
SHDN
C7
2.2 F
SHUTDOWN CONTROL
DISCHARGE
LDO VOLTAGE REGULATOR
VOUT
C1+
C6
4.7 F
C10
C1
3.3 F 3.3 F
CONTROL LOGIC
VOLTAGE DOUBLER
C1-
V CC
VOLTAGE ADDER
C5+
C5
3.3 F
C5DAC1_IN
DAC1_SD
VREF
ADD_OUT
C11 4.7 F
8
CLK DATA
CS / LDAC
DAC 1
INT/EXT DAC 1
+ -
SERIAL INTERFACE
8 DAC 2
INT/EXT DAC 2
TRANS_OUT
C12 4.7 F
COM_IN
LEVEL TRANSLATOR
POWER BUFFER
COM_OUT_AC
C13 4.7 F
+
DAC2_SD DAC2_IN
COM_OUT
-
5.5k
C PA NE L 22nF
GND
ADM8840 FUNCTIONAL BLOCK DIAGRAM
-2-
REV. PrG 2/03
PRELIMINARY TECHNICAL DATA
(VCC = +3V-10%,+20%, TA=-40C to +85C unless otherwise noted ) C1,C5,C10=3.3 F; C2,C3,C4,C8,C9=0.22 F; C6,C11,C12,C13=4.7 F; C7 =2.2 F
PARAMETER Input Voltage,V CC Supply Current,I CC Min 2.7 Typ 3.3 750 5 Max 3.6 Units V uA uA
ADM8840-SPECIFICATIONS
Test Conditions O/Ps Unloaded; COM_IN Low; DAC1_SD, DAC2_SD Low Shutdown Mode DAC1_IN and DAC2_IN should be open circuit because there is a voltage on these pins due to the output of the DAC.
CHARGE PUMP REGULATOR +5.0V OUTPUT Output Voltage Output Current Output Ripple Transient Response +15.0V OUTPUT Output Voltage Output Current Output Ripple -15.0V OUTPUT Output Voltage Output Current Output Ripple Charge-Pump Frequency DIGITAL INPUT PINS Input Voltage, VIH Digital Input Current Digital Input Capacitance COM DRIVER COM_OUT Amplitude Amplitude Stepsize Amplitude Accuracy
4.9
5.0 10 5
5.1 5
V mA mV p-p us V uA mV p-p V uA mV p-p kHz V V A pF
IL = 10uA to 5mA 5mA load IL stepped from 10uA to 5mA IL = 1uA to 100uA I L =100uA IL = -1uA to -100uA I L =-100uA
14.0
15.0 50 50 -15.0 -50 50 100
16.0 150
-16.0 -150 TBD 0.7V CC
-14.0
TBD
0.3VCC 1 10
Note 1.
4 28 <10%
7
V mV %
V COM_OUT =5V; DAC1 loaded with preset values; Measured at TRANS_OUT DAC1 preset values is 1V and Vcom should be 6V
Center Voltage Center Voltage Stepsize Center Voltage Accuracy
0.9
1.8 14 <10%
2.8
V mV %
Rise/Fall Time Center Voltage Settling Time PANEL Load Capacitance POWER EFFICIENCY
1 TBD 20 70
s us nF %
V CENTER =1.8V; DAC2 loaded with preset values DAC2 preset values is 500mV and Vcentre should be 1.5V. C PANEL =20nF
5VOUT Load = 5mA; +/-15V Load = +/-100uA; COM_IN Freq = 10kHz; C PANEL = 20nF; Vcc=2.7V; Note 2
NOTES 1. Guaranteed by Design. Not 100% Production Tested. 2. COM Driver load is defined as the load current flowing through C13 with DACs loaded with preset values. * Specifications are target values and are subject to change without notice.
REV. PrG 2/03
-3-
PRELIMINARY TECHNICAL DATA ADM8840 Timing Specifications
PARAMETER POWER-UP SEQUENCE 5V Rise time, TR5V +15V Rise time, TR15V -15V Fall time, TF15V Delay between VCC rise and SHDN rise, TDELAY1 Delay between -15V fall and +15V rise, TDELAY2 POWER- DOWN SEQUENCE 5V Fall time, TF5V +15V Fall time, TF15V -15V Rise time, TR15V SERIAL INTERFACE t1 t2 t3 t4 t5 t6 t7 Min Typ TBD TBD TBD TBD TBD Max Units us ms ms ms ms
VCC = +3V-10%,+20%, TA=-40C to +85C
Test Conditions /Comments 10% to 90%, Figure 2 10% to 90%, Figure 2 90% to 10%, Figure 2 Figure 2 Figure 2
TBD TBD TBD
ms ms ms
90% to 10%, Figure 2 90% to 10%, Figure 2 10% to 90%, Figure 2
TBD TBD TBD TBD TBD TBD TBD
ns ns ns ns ns ns ns
CS/LDAC falling edge to SCLK Rising Edge; Note 1; Note2 SCLK High Pulsewidth; Note 1; Note2 SCLK Low Pulsewidth; Note 1; Note2 Minumum CS/LDAC high time; Note 1; Note2 SCLK Rising Edge to CS/LDAC Rising Edge; Note 1; Note2 DATA Setup time; Note 1; Note2 DATA Hold time; Note 1; Note2
NOTES 1. Guaranteed by Design. Not 100% Production Tested. 2. See Timing Diagram in Figure 4. * Specifications are target values and are subject to change without notice.
ABSOLUTE MAXIMUM RATINGS*
(TA=25 C unless otherwise noted.)
o
ORDERING GUIDE
Model -0.3 V to +4.0 V -0.3 V to +4.0 V 10 seconds -0.3 V to +6.0 V -17 V to +0.3 V -0.3 V to +17 V -40C to +85C 50mW -65C to +150C Class I
Supply Voltage Input Voltage on Digital Inputs Output Short Circuit Duration to GND Output Voltage +5.0V Output -15.0V Output +15.0V Output Operating Temperature Range Power Dissipation Storage Temperature Range ESD
Temperature Range
Package Option CP-32
ADM8840ACP -40C to +85C
PIN CONFIGURATION
-15VOUT
GND
C2+
C4+
32 31
30 29
28 27
26
25
ADM8840
C1+ 1
C3+
C4-
C1-
C2-
TOP VIEW (NOT TO SCALE)
24 C323 15VOUT 22 VCC
21 C520 C5+
*Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
VCC 2 VOUT 3 5VOUT 4 5VIN 5 SHDN 6 DAC1_SD 7
19 ADD_OUT
18 COM_IN 17 GND
THERMAL CHARACTERISTICS
DAC2_SD 8
32-Lead LFCSP Package: JA = 28C/Watt
9
10 11
12
13 14
15
16
COM_OUT_AC
TRANS_OUT
DAC2_IN
CS/LDAC
DAC1_IN
DATA
SCLK
COM_OUT
-4-
REV. PrG 2/03
PRELIMINARY TECHNICAL DATA ADM8840
PIN FUNCTION DESCRIPTION
Pin 1,32 2, 22 3 4 5 6
Mnemonic C1+,C1V CC VOUT +5VOUT +5VIN SHDN
Function External capacitor C1 is connected between these pins. A 3.3 F capacitor is recommended. Positive Supply Voltage Input. Connect this pin to 3V supply. A 4.7 F decoupling capacitor should be attached close to pin 2. Voltage Doubler Output. This was derived by doubling the 3V supply. A 3.3 F capacitor to ground is required on this pin. +5.0V output pin. This was derived by doubling and regulating the +3V supply. A 2.2 F capcitor to ground is required on this pin to stabilise the regulator. +5.0V input pin. This is the input to the voltage tripler and inverter charge pump circuits. Digital Input. 3V CMOS Logic. Active low shutdown control. This shuts down the timing generator and enables the discharge circuit to dissipate the charge on the voltage outputs, thus driving them to 0V. Switches over to external DAC1 input when asserted. Input for external DAC1 signal. Device Ground Pin. External Clock Input. Used to load DAC 1 with COM Voltage amplitude and DAC 2 with COM Centre Voltage. Digital Data Input to both DAC's 1 and 2. Dual function pin. 1.Chip Select. Digital Input Logic. Chip Select for Digital Interface. 2. Load DAC. Digital Input Logic. DAC's 1 and 2 perform a conversion on a low-to-high transition. Clock Input from digital controller chip. This input is level shifted, offset and inverted to provide a COM Voltage output swing at a frequency of the COM_IN input. COM_OUT_AC outputs the COM_IN signal inverted and level shifted by the value programmed on DAC 1. A 4.7 F capacitor is connected between this pin and COM_OUT. The AC output on COM_OUT_AC is added to the center voltage programmed on DAC2 so that the desired amplitude, centered about the correct center voltage appears on COM_OUT. The load capacitance seen by this pin is the bulk capaci tance of the panel, typically 20nF. Switches over to external DAC2 input when asserted. Input for external DAC2 signal. Level Translator Reference Output Voltage. This is the voltage that the value on DAC 1 is gained up to to provide the upper voltage for the Level Translator. A voltage of between 4.0V and 7.0V can be output here. A 4.7 F cap is recommended for this pin.
7 9 17, 31 13 12 11
DAC1_SD DAC1_IN GND SCLK DATA CS / LDAC
18
COM_IN
16
COM_OUT_AC
14
COM_OUT
8 10 15
DAC2_SD DAC2_IN TRANS_OUT
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADM8840 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
REV. PrG 2/03
-5-
PRELIMINARY TECHNICAL DATA ADM8840
PIN FUNCTION DESCRIPTION (Contd.)
Pin 19
Mnemonic ADD_OUT
Function Voltage Adder Output Pin. (unregulated output of first then used as the supply for Translator Output Voltage. This is voltage generated by adding VOUT stage doubler) to VCC. This summed voltage is the gain stage which generates the Level A 4.7 F capacitor is recommended for this pin. A 3.3 F capacitor is
20,21 23 29,28 25,24 27,26 30
C5+,C5+15VOUT C4+,C4C3+,C3C2+,C2-15VOUT
External capacitor C5 is connected between these pins. recommended.
+15.0V output pin. This was derived by tripling the +5.0V regulated output. A 0.22 F capacitor is required on this pin. External capacitor C4 is connected between these pins. recommended. External capacitor C3 is connected between these pins. recommended. External capacitor C2 is connected between these pins. recommended. A 0.22 F capacitor is A 0.22 F capacitor is A 0.22 F capacitor is
-15.0V output pin. This was derived by inverting the +15.0V output. A 0.22 F capacitor is required on this pin.
POWER SEQUENCING
COM_OUT VOLTAGE
The COM Driver section of the ADM8840 can be used to generate the alternate frame or line inversion of the COM line of the LCD panel. The ADM8840 receives the COM clock (with frequency up to 10kHz) from the controller and allows programmable conditioning of its amplitude and centre voltage through the use of on-board DAC's 1 and 2. This allows programmable elimination of display flicker caused by the COM inversion. The COM_OUT amplitude can be programmed from 4.0V to 7.0V in steps of 28mV. The COM_OUT centre voltage can be programmed from 0.9V to 2.8V in steps of 14mV. Figure 1 below shows a typical output from the COM_OUT pin. If programmable operation is not required the DACs can be shutdown with the DAC1_SD and DAC2_SD pins and an analog voltage applied to the DAC1_IN and DAC2_IN pins to set up the amplitude and centre voltage at COM_OUT.
In order for the TFT panel to power up correctly, the gate drive supplies must be sequenced such that the -15V supply starts up before the +15V supply. The ADM8840 controls this sequence. When the device is turned on, the ADM8840 allow the -15V output to ramp immediately, but holds off the +15V output. It continues to do this until the negative output has reached -3V. At this point, the positive output is enabled and allowed to ramp to +15V. This sequence is highlighted in figure 2.
tDELAY1
VCC SHDN
tR5V
90%
+5V
10%
tF5V
tR15V
90%
4.0Vto7.0V
+15V
0.9V->1.8V->2.8V
10%
tF15V
tDELAY2
0V
-15V
90% 10%
-3V tRM15V tFM15V
A MPL ITUDE : 4 .0V to 7 .0V
CE NTR E V O LT AG E: 0.9 V ->1.8 V->2.8 V
Figure 1. COM_OUT Voltage
COM_OUT
0V
Figure 2. Power Sequence
-6-
REV. PrG 2/03
PRELIMINARY TECHNICAL DATA ADM8840
SERIAL INTERFACE
The COM Driver section of the ADM8840 uses a serial interface to input data and transfer it into the DACs. Figure 3, below, shows the operation of the serial interface. The data is transmitted along the serial DATA line, along with a serial clock signal, SCLK. This data is read into a Shift Register. When the 8 bits are sucessfully stored in the Shift Register a low-to-high transition on the CS/LDAC input causes the latch to load the 8-bits of data into the relevent DAC. This function is also shown in the waveforms in Figure 4 below. A falling edge on the CS/LDAC input initiates the data read into the shift register. The first bit of the datastream is the DAC Select Bit (DAC_SEL) which determines which internal DAC the data will be written to. A `1' selects DAC 1 which sets the Amplitude of the output and a `0' selects
DAC 2 which sets the Centre Voltage of the output. The individual data bits are then read in one by one on the DATA line. After the DAC_SEL bit and the 8 data bits have been read there is a pause to ensure the shift register outputs are stable. Then a rising edge on the CS/LDAC input loads the 8 bits on the shift register outputs into the relevent DAC (and the DAC outputs will change accordingly). Note that if CS/ LDAC goes high before all 8 data bits are read in then incorrect data will be loaded into the DACs. All bits on the DATA line are read in on each rising edge of the SCLK signal. When the ADM8840 comes out of shutdown the DACs are preset with default values generating a COM_OUT Amplitude of 6V with a Centre voltage of 1.5V.
8 DATA BITS
DATA
SHIFT REGISTER
DAC 1 LATCH
DAC 1 (AMPLITUDE)
DAC 1 OUT
SCLK
DAC_SEL BIT
DAC 2 LATCH
DAC SELECT
DAC 2 (CENTRE VOLTAGE)
DAC 2 OUT
CS/LDAC
Figure 3. Serial Interface Diagram
t1 t2
t3
t4
CS / LDAC
SCLK
DATA
D AC SEL
D0
D1
D2
D3
D4
D5
D6
D7
t7
t6
t5
Figure 4. Serial Interface Waveforms
REV. PrG 2/03
-7-
PRELIMINARY TECHNICAL DATA ADM8840
DAC1 Setup The resolution of DAC1 is 4.7mV this is scaled up by 6 to give COM_OUT amplitude resolution of 28mV (4.7mV * 6 = 28mV). The COM_OUT amplitude Vp-p is given by, (Binary Code/255)(1.188)(6)= Vp-p (COM_OUT). A table of the min, max and typical values for COM_OUT amplitude is given in the Table 1 below. DAC2 Setup The resolution of DAC2 is 4.7mV this is scaled up by 3 to give you the COM_OUT centre voltage resolution of 14mV (4.7mV * 3 = 14mV). The COM_OUT centre voltage is given by, (Binary Code/255)(1.188)(3)= COM_OUT DC Voltage. A table of the min, max and typical values for COM_OUT centre voltage is given in the Table 2 below.
Table 1 COM_OUT amplitude Voltage COM_OUT amplitude voltage (Max) 7.016V 6.9882 ......... (Typ) 6.0098V .......... 4.0531V (Min) 4.0025V Binary Bits written to DAC1 11111011 11111010 ............. 11010111 ............. 10010001 10010000 Table 2 COM_OUT centre voltage COM_OUT centre voltage (Max) 2.8092V 2.7952V ........... 1.5094V ........... (Min) 0.9224V 0.9084V Binary Bits written to DAC2 11001001 11001000 .............. 01101100 .............. 01000010 01000001 Integer 201 200 ...... 108 ...... 66 65 DAC2_IN Voltage 933mV 928mV .......... 503.9mV .......... 304.7mV 300mV Integer 251 250 ..... 215 ..... 145 144 DAC1_IN Voltage 1.667V 1.6623 ........... 1.0011V ........... 671.7mV 667mV
(Typ)
-8-
REV. PrG 2/03
PRELIMINARY TECHNICAL DATA ADM8840
BOOSTING THE CURRENT DRIVE OF THE +/-15V SUPPLY The ADM8840 +/-15V output can deliver 100uA of current in the typical configuration, as shown in Figure 5. In this configuration the 5Vout (pin 4) is connected to 5Vin (pin 5), as can be seen on block diagram Page 1 of this data sheet.
It is possible to configure the ADM8840 to supply up to 400uA on the +/-15V outputs, by changing its configuration slightly, as shown in Figure 6.
-15V
VOLTAGE INVERTER
C4+
C4 0.22 F
C9
0.22 F
C4-
ADM8840
TRIPLE VOLTAGE TRIPLER DOUBLE
+15V
C2+
C2 0.22 F
C8
0.22 F
C2C3+
C3
0.22 F
C3-
OSCILLATOR
TIMING GENERATOR
Current Boost Configuration Connection
+5V
5VIN
5VOUT
SHDN
C7
2.2 F
SHUTDOWN CONTROL
DISCHARGE
LDO VOLTAGE REGULATOR
VOUT
-15V
C1+
VOLTAGE INVERTER
C4+
C4 0.22 F C9
0.22 F
C10
C1 3.3 F
3.3 F
C6
4.7 F
CONTROL LOGIC
VOLTAGE DOUBLER
C1-
C4-
ADM8840
TRIPLE VOLTAGE TRIPLER DOUBLE
+15V
V CC
0.22 F
C5+
C2+
C2 0.22 F
C8
VOLTAGE ADDER
C5DAC1_IN
C5
3.3 F
C2C3+
C3
0.22 F
DAC1_SD
C3-
OSCILLATOR
TIMING GENERATOR
5VIN +5V
VREF
ADD_OUT
5VOUT
SHDN
C7
2.2 F
CLK DATA
CS / LDAC
8
SHUTDOWN CONTROL
DISCHARGE
LDO VOLTAGE REGULATOR
DAC 1
INT/EXT DAC 1
+ -
C11 4.7 F
SERIAL INTERFACE
8 DAC 2
INT/EXT DAC 2
VOUT
TRANS_OUT
C12 4.7 F
C1+
C6
4.7 F
C10
C1 3.3 F
3.3 F
COM_IN
CONTROL LOGIC
VOLTAGE DOUBLER
C1-
LEVEL TRANSLATOR
PO WER BUFFER
COM_OUT_AC
C13 4.7 F
V CC
VOLTAGE ADDER
C5+
C5
3.3 F
+
DAC2_SD DAC2_IN
COM_OUT
C5DAC1_IN
-
5k
C PANEL
22nF
DAC1_SD
VREF
ADD_OUT
8
CLK DATA
CS / LDAC
DAC 1
INT/EXT DAC 1
+ -
C11 4.7 F
GND
SERIAL INTERFACE
8 DAC 2
INT/EXT DAC 2
TRANS_OUT
C12 4.7 F
Figure 6. Current Boost Configuration
COM_IN
LEVEL TRANSLATOR
POWER BUFFER
COM_OUT_AC
C13 4.7 F
+
DAC2_SD
COM_OUT
DAC2_IN
5k
C PANE L
22nF
The configuration in Figure 6, can supply up to 400uA of current on both the +15V and the -15V outputs. If the load on the +/-15V does not draw any current the voltage on the +/-15V outputs can rise up to +/-16.5V.In this configuration Vout (pin 3) is connected to 5Vin (pin 5).
GND
Figure 5. Typical Configuration
REV. PrG 2/03
-9-
PRELIMINARY TECHNICAL DATA ADM8840
OUTLINE DIMENSIONS
Dimensions Shown in Inches and (mm).
32-Lead 5X5 Chip Scale Package (CP-32)
0.197 (5.0) BSC SQ 0.024 (0.60) 0.017 (0.42) 0.009 (0.24) 0.024 (0.60) 0.017 (0.42) 25 0.009 (0.24) 24 0.010 (0.25) MIN
32
1
PIN 1 INDICATOR
TOP VIEW
0.187 (4.75) BSC SQ
0.012 (0.30) 0.009 (0.23) 0.007 (0.18) 0.020 (0.50) 0.016 (0.40) 0.012 (0.30)
17 16
BOTTOM VIEW
0.128 (3.25) 0.122 (3.10) SQ 0.116 (2.95)
98
12. MAX 0.035 (0.90) MAX 0.033 (0.85) NOM SEATING PLANE 0.020 (0.50) BSC
0.031 (0.80) MAX 0.026 (0.65) NOM
0.138 (3.50) REF
0.008 (0.20) REF
0.002 (0.05) 0.0004 (0.01) 0.0 (0.00)
-10-
REV. PrG 2/03

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